In order to analyze and effect redundancy to repair defective memory rows and/or columns of a memory device (e.g., a RAM), all fail information with respect to the memory array of the device must be captured and analyzed. Several approaches are known in the art:
U.S. Pat. No. 4,456,995 (Ryan; assigned to the assignee of the present application) discloses an approach wherein a counter is provided which is capable of providing a count value up to the number of bits in a RAM under test, and wherein there is a counting of fails by word line, and then by bit line in a two pass test.
U.S. Pat. No. 4,460,999 (Schmidt; related to the '997 Harns patent); U.S. Pat. No. 4,460,997 (Harns; related to the '999 Schmidt patent) disclose approaches which employ an error capture RAM which is configured both in size and arrangement to mirror those of a RAM under test. Testing is conducted, and any memory failures which occur along the memory array are recorded in a corresponding location in the error capture RAM. In order to extract the fail information from the error capture RAM to perform redundancy analysis, time-consuming software routines or special hardware is required.
The just-discussed conventional apparatus and method are disadvantageous in that, error capture RAMs increase in cost as the device under test (DUT) grows in size, and in addition, the extraction of fail information also grows in complexity, typically requiring several passes through the error capture RAM resulting in substantial time consumption.
U.S. Pat. No. 4,586,178 (Bosse; related to the Bosse '915 patent) and U.S. Pat. No. 4,639,915 (Bosse; related to the Bosse '178 patent) are directed to array testing apparatus for determining fail positions, and a method for replacing the fails with redundant lines. An analog summer is used to count the fails and the failed row and column addresses are stored in separate parallel lists requiring both addresses to be stored for each fail. Such arrangement causes the speed of the Bosse circuit to be lowered because of cycle time, and also causes bit failure address latches and a fail matrix to be substantially large.
U.S. Pat. No. 4,627,053 (Yamaki et al) discloses a method of repairing a semiconductor memory device having spare lines. All possible solutions of remedy using spare lines or spare blocks are obtained via analysis of the result of a test of the device, and then all possible solutions are screened under conditions related to the quality and reliability of the device so as to determine a best solution.
U.S. Pat. No. 4,628,509 (Kawaguchi) discloses an array testing apparatus designed to replace failed lines with redundant lines, by utilizing RAMs as look-up tables for storing fails. Disadvantages are present as there is a slowing of a speed of the circuit, and also, the fail counters are arranged such that there is a potential that some fails will be missed.
JP 52-67227 (Takezono) discloses a memory unit wherein failure areas which occur in clusters are collected together and memorized by an auxiliary memory.
Further approaches of background interest are described in: JP 55-28119 (Narumi); JP 55-34380 (Narumi); JP 56-61100 (Aida); JP 55-113200 (author unknown); JP 56-73354 (author unknown); JP 56-73355 (author unknown); JP 56-84056 (author unknown); JP 56-124200 (Nozaki); JP 56-130899 (author unknown); JP 57-88600 (Ishiguro); JP 57-130295 (Nigorikawa); JP 57-164497 (Miyazaki); JP 57-164500 (Eguchi); JP 58-115698 (Nishimoto); JP 59-207497 (author unknown); JP 60-70375 (author unknown); JP 60-167199 (Matsuoka); JP 61-68800 (author unknown); JP 61-80070 (author unknown); JP 60-167200 (author unknown); JP 61-199300 (Sueyoshi); JP 61-271700 (author unknown).